Balanced integrate and dump circuit for measuring duty cycle of a pulse train

ABSTRACT

A balanced integrate and dump circuit includes a first integrator, differential amplifier, second integrator and timing circuit, for detecting the presence or absence of pulse train signals in a predetermined time interval, determining whether the pulse train signals are present for greater than a predetermined percentage of the time interval measured and resetting the circuit for the next measurement. Differential comparison of voltages representing the presence and absence of pulses in the measured time interval eliminates errors due to timing period variations, voltage variations, imperfect pulse train signals and circuit operating characteristics.

United States Patent [72] Inventor Eugene J. Bruckert [56] ReferencesCited 21 A I N 3835? UNITED STATES PATENTS f M8 1969 3,048,708 8/1962Raver 307/293 [45] Patented 1971 3,441,874 4/1969 Bennett 307/228 x [73]Assi nee g Inc 3,210,558 10/1965 Owen 307/228 2 Franklin i 1 3,375,5013/1968 McCutcheon et al. 328/151 X r 3,473,133 10/1969 Hummel 307/233 XPrimary Examiner- Stanley D. Miller, Jr. 154] BALANCED INTEGRATE ANDDUMP CIRCUIT A!!0rneyMueller & Aichele FOR MEASURING DUTYCYCLE OF APULSE TRAIN 5 Claims, 1 Drawing Fig, ABSTRACT: A balanced integrate anddump circuit includes a first integrator, differential amplifier, secondintegrator and [52] U.S.Cl 307/234, timin circuit for detect, theresence or absence of U156 307/229 307/232 307/235 324/78R 328/111 8 g pp 328 8 train signals in a predetermined time interval, determining [511 Int Cl H03k whether the pulse train signals are present for greaterthan a 1501 Field of Search 307/231, predemmmed percentage the 'memlmeasured and OUTPUT resetting the circuit for the next measurement.Differential comparison of voltages representing the presence andabsence of pulses in the measured time interval eliminates errors due totiming period variations, voltage variations, imperfect pulse trainsignals and circuit operating characteristics.

OUTPUT l I I 3! I I it I V 14 52 I l L I l 19 l I58 I INVERTER LIMITER67 PULSE TRAiN INPUT PATENTEnuuv 30 Ian OUTPUT INVERTER LIMiTER V67PULSE TRAIN INPUT ATTYS BALANCED INTEGRATE AND DUMP CIRCUIT FORMEASURING DUTY CYCLE OF A PULSE TRAIN BACKGROUND OF THE INVENTION Incommunication systems it is often necessary to measure the duty cycle ofa pulse train, having pulses of a predetermined maximum and minimumamplitude, in a predetermined period. An example of such use is in adigital communication system where information bits must be sensed inthe presence of noise signals which tend to mask the presence of theinformation bits. The duty cycle of a pulse train, consisting of pertions of the information bit not masked by the noise signal, and noisepulses, is measured for a time period equivalent to the length of aninformation bit. If the duty cycle of the pulse train exceeds 50 percentof the measured period, an information bit is assumed present. Integrateand dump circuits have been employed which integrate a pulse train todevelop a voltage proportional to the duty cycle. The voltage iscompared to a reference voltage of a desired value, representing adesired duty cycle, to provide an output function or voltage change,indicating whether the pulse train duty cycle exceeds or falls below thedesired duty cycle. The desired reference voltage is provided by aresistor divider network or a diode, coupled to the reference input of adifference comparison device. This method of comparison has thedisadvantage that changes in voltage levels due to supply voltagevariation, or changes in operating characteristics of the circuit withtemperature, cause a variation in the reference voltage which results inan erroneous comparison and output reading. Variations in the measuredtime interval and imperfect square wave signals having a finite rise andfall time create errors when the summed voltage is compared to apredetermined voltage, the value of which was determined based on apulse with a predetermined amplitude, constant time period, and zerorise and fall time.

Balanced detector circuits which compare portions of pulse train signalshave been designed to convert pulse train signals to a DC voltage thatvaries in proportion to the duty cycle of the pulse train. When used asan analog rather than digital circuit, the output variation iscontinuously monitored which precludes the use of the reset function ofthe comparison voltages. As an analog device, the integration circuitemployed does not produce as close an approximation to a trueintegration function as is required in a digital circuit. Where thecontinuous variation in an average voltage is of interest, theintegration voltage developed need not be held constant at the levelestablished at the end of the last pulse train.

SUMMARY OF THE INVENTION It is, therefore, an object of this inventionto provide a balanced integrate and dump circuit which is lesssusceptable to errors due to a change in supply voltage levels.

Another object of this invention is to provide a balanced integrate anddump circuit which is less susceptable to errors due to a change inoperating characteristics of the circuit with temperature changes.

Yet another object of the invention is to provide a balanced integrateand dump circuit which cancels errors due to variation in the rise andfall times ofthe square wave input signals.

A further object of the invention is to provide a balanced integrate anddump circuit which is not susceptable to error due to changes in themeasured time intervals.

Another object of this invention is to provide a balanced integrate anddump circuit having circuitry which closely approximates a trueintegration function.

Yet another object of this invention is to provide a balanced integrateand dump circuit whose developed integration voltage remains constant,at the level established at the end of the last square wave in the pulsetrain, until the end of the measured time interval.

In practicing the invention, a balanced integrate and dump circuit isprovided wherein, at a predetermined time, a clock circuit dischargesvoltages developed in two integrators. Pulse train signals of the pulsetrain to be measured which have a minimum and maximum amplitude arecoupled to a first integrator to develop an integration voltage which isa function of the percentage of time the pulse train signals are at theminimum amplitude in the measured time interval. The pulse train is alsoinverted to produce a resultant pulse train which is coupled to a secondintegrator to develop an integration voltage which is a function of thepercentage of time the resultant pulse train is at the minimum amplitudein the measured time interval. This is proportional to the amount oftime the pulses of the original pulse train are at a maximum amplitudein the measured time interval. The integration voltages developed in thefirst and second integrators are then coupled to separate inputs of adifferential amplifier. If the voltage developed in the first integratorexceeds the voltage developed in the second integrator, the voltagelevel at the first output of the differential amplifier will decrease.If the second integration voltage exceeds the first integration voltage,the voltage level at a second output of the differential amplifier willdecrease. At the end of the measured time interval the voltage levels atthe outputs of the differential amplifier indicate whether the firstintegration voltage exceeds the second integration voltage therebyindicating whether the pulse train was present for more than or lessthan a predetermined percentage of the measured time interval. At thesame time the timing circuit resets, discharging the voltages developedin both integrators and starting a new measurement interval.

BRIEF DESCRIPTION OF THE DRAWING The single FIGURE of the drawing is acombination schematic and block diagram of the balanced integrate anddump circuit of this invention.

DETAILED DESCRIPTION OF THE INVENTION Referring to the drawing there isshown a balanced integrate and dump circuit including a first integrator60, differential amplifier 61, second integrator 62, and a timingcircuit consisting of transistors 20 and 45.

A clock pulse having a predetermined amplitude, period and repetitionrate is coupled from a clock circuit 65 to bases 21 and 46 oftransistors 20 and 45, through terminal 33 and resistors 30 and 49. Theclock pulse biases transistors 20 and 45 to saturation therebydischarging integration capacitors l9 and 50 in integrators 60 and 62.This sets the basic timing of the circuit and resets the integrate anddump circuit. The pulse train which is to be measured, and whichalternates between a constant amplitude positive voltage level and zerovoltage, is coupled from limiter 67 to base 14 of transistor currentsource 13 through terminal 11 and resistor 12, The zero voltage portionsof the pulse train cause transistor current source 13 to saturateallowing capacitor I9 to charge at a constant rate. The combination oftransistor current source 13 and capacitor 19 will produce a very closeapproximation to an integration function.

The positive voltage portions of the pulse train will cause transistorcurrent source 13 to be cut off. Voltage developed across capacitor 19when transistor current source 13 is ON, is a function of the percentageof time that the zero voltage portions of the pulse train are present inthe measured time interval.

Pulse train signals from limiter 67 are also coupled to inverter 66where they are inverted to produce a resultant pulse train which is thencoupled from inverter 66 to base 52 of transistor 51 through terminal 59and resistor 58. The zero voltage portions of the resultant pulse traincauses transistor current source 51 to saturate thereby chargingcapacitor 50 at a constant rate. The positive voltage portions of theresultant pulse train cause transistor current source 51 to be cut off,The voltage developed across capacitor 50 when transistor current source51 is ON is a function of the percentage of time the zero voltageportion of the resultant pulse train is present in the measured timeinterval. This corresponds to the percentage of time that the positivevoltage portions of the original pulse train are present in the measuredtime interval.

Capacitors l9 and 50 have no discharge path therefore the voltagedeveloped across the capacitors when transistor current sources 13 and51 are ON will remain constant until the transistor current sources areagain turned on, further charging their respective capacitors, or untiltransistors 20 and 45 reset the circuit.

The voltages developed across capacitors 19 and 50 are coupled to bases35 and 39 respectively of transistors 34 and 38 of differentialamplifier 61. Transistor 25 in differential amplifier 61 acts as acurrent limiter for transistors 34 and 38.

If the voltage developed at base 35 of transistor 34 exceeds the voltageat base 39 of transistor 38, the voltage at collector 37 of transistor34 will decrease below a predetermined level causing transistor 42 to beforward biased thereby reducing the voltage at emitter 43 of transistor42 below a predetermined level. If the voltage developed at base 39 oftransistor 38 exceeds the voltage developed at base 35 of transistor 34,the voltage at collector 41 of transistor 38 will decrease below apredetermined level causing transistor 47 to be forward biased therebyreducing the voltage at emitter 48 of transistor 47 below apredetermined level. At the end of the measured time interval thevoltages at collector 37 of transistor 34 and collector 4] of transistor38 indicate which capacitor, 19 or 50, has a greater voltage across it.This allows determination of whether the duty cycle of the pulse trainwas greater than or less than a predetermined desired duty cycle. At thesame time, a clock pulse is again coupled to terminal 33 causingtransistors 20 and 45 to saturate, discharging the voltages developedacross capacitors l9 and 50, resetting the circuit, and starting a newmeasurement,

lf transistor current sources 13 and 51 supply current to capacitors 19and 50 at an identically constant rate, and transistor current sources13 and 51 are each turned on for the same amount of time in the measuredtime interval, the voltages developed across capacitors 19 and 50 inintegrators 60 and 62 at the end of the measured time interval will beequal. For transistor current sources 13 and 51 to be ON the same amountof time in the measured time interval, the duty cycle of the pulse trainmust be 50 percent of the measured time interval.

If it is desired to determine a different duty cycle of the pulse trainthe following formulas are used:

l l 1 l I =the current supplied by transistor current source 13 inintegrator 60. V the voltage developed across capacitor 19 in integrator60. 7 C the capacitance of capacitor 19 in integrator 60.

I, the time that the transistor current source 13 in integrator 60 isON. The second formula is:

2 22u 2 l =the current supplied by transistor current source 51 inintegrator 62. V =voltage developed across capacitor 50, 1 =the timethat transistor current source 51 in integrator 62 is ON. C =thecapacitance of capacitor 50 in integrator 62.

For example, if it is desired to determine whether the duty cycle of thepulse train is greater than three quarters of the measured timeinterval, the current sources are regulated so that at a time t, whichrepresents the end of the measured time interval, the voltage developedon capacitors l9 and 50 will be equal and t,=3t/4; t =l/4.

Replacing I, and 1 in equations l and 2 by their equivalent in termsoft, then:

(1,3t)/4--V,=V =l,t)/4C and: 3I,=l

The current from the transistor current source must, therefore, equalthree times the current from transistor current source 13. Values ofresistors 17 and 55 may be varied to provide the required current. Acorresponding equation may be usedfor an duty cycle measurementdesired.

Thus, a ba anced integrate and dump circuit has been shown. By thismeans a voltage comparison is made differentially whereas errors due totiming, period variation, voltage variation, imperfect square wavesignals and the circuit operating characteristics are common mode andwill be canceled in the differential amplifier circuit.

lclaim:

1. An integrate and dump circuit for measuring the duty cycle of a pulsetrain, including in combination, input means adapted to receive thepulse train and to develop therefrom first and second trains of pulsesignals with said second train of pulse signals being the inverse ofsaid first train of pulse signals, first and second integration meanseach coupled to said input means and having a transistor biased toconduct in response to a voltage exceeding a predetermined level, timingmeans coupled to said first and second integration means for developinga timing signal to reset said first and second integration means to areference voltage after a predetermined time period, said firstintegration means being responsive to said first train of pulse signalsduring said predetermined period to develop and maintain a first voltageproportional to the duty cycle of the first train of pulse signals, saidsecond integration means being responsive to said second train of pulsesignals during said predetermined period to develop and maintain asecond voltage proportional to the duty cycle of the second pulse train,difference comparison means including transistor current limiting meanscoupled to said first and second integration means and responsive tosaid first and second voltages to develop a comparison signal indicatingwhich of said first and second voltages is greater.

2. The integrate and dump circuit of claim 1 wherein said differencecomparison means includes a differential amplifier, said differentialamplifier having a first input coupled to said first integration meansand a second input coupled to said second integration means, saidtransistor current limiting means being coupled to said differentialamplifier for limiting the current therethrough, said differentialamplifier comparing said first and second voltages and developing asignal in dicating which of said first and second voltages is greater,thereby determining whether the duty cycle of the pulse train exceeds apredetermined percentage of the predetermined period.

3. The integrate and dump circuit of claim 1 wherein said transistors ofsaid first and second integration means each forms current source meansresponsive to its particular train of pulse signals and includingreactance means coupled to said current source means, said currentsource means and reactance means acting in combination to develop avoltage from said particular train of pulse signals which is a functionof the duty cycle of said particular train of pulse signals.

4. The integrate and dump circuit of claim 1 wherein said transistors ofsaid first and second integration means each forms transistor currentsource means, each of said transistor current source means having acontrol electrode adapted to receive said particular train of pulsesignals, a capacitor coupled to said transistor current source means,said current source means and capacitor means acting in combination todevelop a voltage from said particular train of pulse signals which is afunction of the duty cycle of said particular train of pulse signals.

5. The integrate and dump circuit of claim 1, wherein said timing meansincludes clock means, a first transistor having a first electrodecoupled to said first integration means, a second electrode coupled to areference potential and a control electrode coupled to said clock means,a second transistor having a first electrode coupled to said secondintegration means, a second electrode coupled to said referencepotential and a control electrode coupled to said clock means, saidfirst and second transistors being responsive to said timing signal toreset said first and second integration means after a predeterminedperiod of time.

1. An integrate and dump circuit for measuring the duty cycle of a pulsetrain, including in combination, input means adapted to receive thepulse train and to develop therefrom first and second trains of pulsesignals with said second train of pulse signals being the inverse ofsaid first train of pulse signals, first and second integration meanseach coupled to said input means and having a transistor biased toconduct in response to a voltage exceeding a predetermined level, timingmeans coupled to said first and second integration means for developinga timing signal to reset said first and second integration means to areference voltage after a predetermined time period, said firstintegration means being responsive to said first train of pulse signalsduring said predetermined period to develop and maintain a first voltageproportional to the duty cycle of the first train of pulse signals, saidsecond integration means being responsive to said second train of pulsesignals during said predetermined period to develop and maintain asecond voltage proportional to the duty cycle of the second pulse train,difference comparison means including transistor current limiting meanscoupled to said first and second integration means and responsive tosaid first and second voltages to develop a comparison signal indicatingwhich of said first and second voltages is greater.
 2. The integrate anddump circuit of claim 1 wherein said difference comparison meansincludes a differential amplifier, said differential amplifier having afirst input coupled to said first integration means and a second inputcoupled to said second integration means, said transistor currentlimiting means being coupled to said differential amplifier for limitingthe current therethrough, said differential amplifier comparing saidfirst and second voltages and developing a signal indiCating which ofsaid first and second voltages is greater, thereby determining whetherthe duty cycle of the pulse train exceeds a predetermined percentage ofthe predetermined period.
 3. The integrate and dump circuit of claim 1wherein said transistors of said first and second integration means eachforms current source means responsive to its particular train of pulsesignals and including reactance means coupled to said current sourcemeans, said current source means and reactance means acting incombination to develop a voltage from said particular train of pulsesignals which is a function of the duty cycle of said particular trainof pulse signals.
 4. The integrate and dump circuit of claim 1 whereinsaid transistors of said first and second integration means each formstransistor current source means, each of said transistor current sourcemeans having a control electrode adapted to receive said particulartrain of pulse signals, a capacitor coupled to said transistor currentsource means, said current source means and capacitor means acting incombination to develop a voltage from said particular train of pulsesignals which is a function of the duty cycle of said particular trainof pulse signals.
 5. The integrate and dump circuit of claim 1, whereinsaid timing means includes clock means, a first transistor having afirst electrode coupled to said first integration means, a secondelectrode coupled to a reference potential and a control electrodecoupled to said clock means, a second transistor having a firstelectrode coupled to said second integration means, a second electrodecoupled to said reference potential and a control electrode coupled tosaid clock means, said first and second transistors being responsive tosaid timing signal to reset said first and second integration meansafter a predetermined period of time.